ASIC Digital Design Verification Engineer

Proto is accelerating the world's transition to an open economy with products that increase access and independence for everyone. We're building Bitkey, a simple and safe self-custody bitcoin wallet that will put customers in control, as well as hardware and software that will help decentralize bitcoin mining and enable new and innovative use cases for bitcoin mining. We're developing these products in the open - you can read more about them at bitkey.build and mining.build. Within Proto, our Bitcoin Products team delivers the product and go-to-market strategy, software, firmware, and custom silicon needed to make Bitkey and our ambitious mining initiatives a reality. Come build the future of money with us!

As an ASIC Digital Design Verification Engineer, you will work closely with other digital designers and physical designers to develop the next generation of mining ASIC. In particular, the challenges of chip/block simulation, emulation and verification are critical parts of this role.

Key Responsibilities

• Block- and Chip-Level Verification: Develop and execute comprehensive test plans for individual IP blocks and full-chip integrations.
• Gate-Level Simulation & Debug: Run gate-level simulations, analyze netlists, and diagnose timing or logic issues.
• Silicon Bring-Up & Lab Debug: Support bring-up activities in the lab, perform board-level bring-up, and troubleshoot silicon on hardware using oscilloscopes, logic analyzers, etc.
• Automation & Scripting: Create and maintain scripts to streamline verification flows (e.g., regression, coverage collection, and reporting).
• Cross-Functional Collaboration: Work closely with RTL designers, physical design, firmware, and system teams to resolve issues quickly and efficiently.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of hands-on experience in digital ASIC verification.
• Strong knowledge of verification methodologies, particularly UVM.
• Proficiency with EDA tools such as Synopsys VCS, Verdi, and waveform viewers.
• Solid experience with gate-level simulation.
• Experience with silicon bring-up and lab tools (oscilloscopes, logic analyzers, etc.).
• Proficiency in scripting languages (Python, Perl, Tcl, Make).
• Strong problem-solving and analytical skills with attention to detail.

Preferred Qualifications

• Master's degree in Electrical or Computer Engineering.
• Familiarity with serial interfaces such as UART
• Experience with common SoC IPs (PLL,GPIO etc)
• SystemVerilog RTL design experience.
• Exposure to full-chip emulation environments (e.g., Synopsys ZeBu).
• Hands-on experience with FPGA prototyping tools (e.g., Xilinx Vivado).

We're working to build a more inclusive economy where our customers have equal access to opportunity, and we strive to live by these same values in building our workplace. Block is an equal opportunity employer evaluating all employees and job applicants without regard to identity or any legally protected class. We will consider qualified applicants with arrest or conviction records for employment in accordance with state and local laws and “fair chance” ordinances.

We believe in being fair, and are committed to an inclusive interview experience, including providing reasonable accommodations to disabled applicants throughout the recruitment process. We encourage applicants to share any needed accommodations with their recruiter, who will treat these requests as confidentially as possible. Want to learn more about what we're doing to build a workplace that is fair and square? Check out our I+D page.

While there is no specific deadline to apply for this role, U.S. roles are typically open for an average of 55 days before being filled by a successful candidate. Please refer to the date listed at the top of this job page for when this role was first posted.